PC912XDP512F0MPVR datasheet(610/1348 Pages) FREESCALE

610 / 1348 page

Chapter 16 Interrupt (S12XINTV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

610

Freescale Semiconductor

16.5

Initialization/Application Information

16.5.1

Initialization

After system reset, software should:

•

Initialize the interrupt vector base register if the interrupt vector table is not located at the default

location (0xFF10–0xFFF9).

•

Initialize the interrupt processing level conﬁguration data registers (INT_CFADDR,

INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request

target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.

•

If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and

conﬁgure the XGATE module (please refer the XGATE Block Guide for details).

•

Enable I maskable interrupts by clearing the I bit in the CCR.

•

Enable the X maskable interrupt by clearing the X bit in the CCR (if required).

16.5.2

Interrupt Nesting

The interrupt request priority level scheme makes it possible to implement priority based interrupt request

nesting for the I bit maskable interrupt requests handled by the CPU.

•

I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,

so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to

Figure 16-14 for an example using up to three nested interrupt requests).

I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per

default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the

I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can

interrupt the current ISR.

An ISR of an interruptible I bit maskable interrupt request could basically look like this:

•

Service interrupt, e.g., clear interrupt ﬂags, copy data, etc.

•

Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with

higher priority)

•

Process data

•

Return from interrupt by executing the instruction RTI

PC912XDP512F0MPVR 데이터시트(PDF) 610 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 610 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL