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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 642 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 642 Page - Freescale Semiconductor, Inc |
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642 / 1348 page  Chapter 17 Memory Mapping Control (S12XMMCV2) MC9S12XDP512 Data Sheet, Rev. 2.21 642 Freescale Semiconductor 17.4.4 Chip Bus Control The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping operations. All internal and external resources are connected to specific target buses (see Figure 1-26). Figure 17-26. S12X Architecture 17.4.4.1 Master Bus Prioritization The following rules apply when prioritizing accesses over master buses: • The CPU has priority over the BDM, unless the BDM access is stalled for more than 128 cycles. In the later case the CPU will be stalled after finishing the current operation and the BDM will gain access to the bus. • XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU and BDM for its duration. XBus2 CPU P0 P1 P2 P3 XFLASH XEEPROM IPBI EBI XBus0 ROM/REG BDM IO XBus1 RAM XRAM 2 Kbyte Registers S12X S12X XGATE MMC BDM XGATE |
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