PC912XDP512F0MPVR datasheet(644/1348 Pages) FREESCALE

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Chapter 17 Memory Mapping Control (S12XMMCV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

644

Freescale Semiconductor

This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction

execution. A CALL instruction can be performed from any address to any other address in the local CPU

memory space.

The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing

mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand

in the instruction. In indexed-indirect variations of the CALL instruction a pointer speciﬁes memory

locations where the new page value and the address of the called subroutine are stored. Using indirect

addressing for both the new page value and the address within the page allows usage of values calculated

at run time rather than immediate values that must be known at the time of assembly.

The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks

the PPAGE value and the return address and reﬁlls the queue. Execution resumes with the next instruction

after the CALL instruction.

During the execution of an RTC instruction the CPU performs the following steps:

1. Pulls the previously stored PPAGE value from the stack

2. Pulls the 16-bit return address from the stack and loads it into the PC

3. Writes the PPAGE value into the PPAGE register

4. Reﬁlls the queue and resumes execution at the return address

This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory

space.

The CALL and RTC instructions behave like JSR and RTS instruction, they however require more

execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and

CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to

access subroutines that are already present in the local CPU memory map (i.e. in the same page in the

program memory page window for example). However calling a function located in a different page

requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because

the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the

RTC instruction must be called using the CALL instruction even when the correct page is already present

in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time

of the RTC instruction execution.

17.5.2

Port Replacement Registers (PRRs)

Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full

emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see

Table 1-25). PRRs are accessible from all masters using different access types (word aligned,

word-misaligned and byte). Each access to PRRs will be extended to 2 bus cycles for write or read accesses

independent of the operating mode. In emulation modes all write operations result in writing into the

internal registers (peripheral access) and into the emulated registers (external access) located in the PRU

in the emulator at the same time. All read operations are performed from external registers (external

access) in emulation modes. In all other modes the read operations are performed from the internal

registers (peripheral access).

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