PC912XDP512F0MPVR datasheet(716/1348 Pages) FREESCALE

716 / 1348 page

Chapter 19 S12X Debug (S12XDBGV2) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

718

Freescale Semiconductor

19.4.2.3.2

Outside Range (Address < CompAC_Addr or Address > CompBD_Addr)

In the outside range comparator mode, either comparator pair A and B or comparator pair C and D can be

conﬁgured for range comparisons. A single match condition on either of the comparators is recognized as

valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned

address is outside the range.

Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are

from an unexpected range. In forced trigger modes the outside range trigger would typically be activated

at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to

0x7FFFFF or lower range limit to 0x000000 respectively.

When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by

the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR

19.4.3

Trigger Modes

Trigger modes are used as qualiﬁers for a state sequencer change of state. The control logic determines the

trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in

the following sections.

19.4.3.1

Trigger On Comparator Match

If a comparator match occurs, a trigger occurs to initiate a transition to another state sequencer state and

the corresponding ﬂags in DBGSR are set. For a comparator match to trigger ﬁrstly the comparator must

be enabled by setting the COMPE bit in the corresponding comparator control register. Secondly the state

control register for the current state must enable the match for that state. The state control registers allow

for different matches to be enabled in each of the states 1 to 3.

19.4.3.2

Trigger On Comparator Related Taghit

If either a CPU or XGATE taghit occurs a transition to another state sequencer state is initiated and the

corresponding DBGSR ﬂags are set. For a comparator related taghit to occur, the DBG must ﬁrst generate

tags based on comparator matches. When the tagged instruction reaches the execution stage of the

instruction queue a taghit is generated by the CPU/XGATE.

19.4.3.3

External Tag Trigger

In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an

instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the

execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session

and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device

emulation modes.

PC912XDP512F0MPVR 데이터시트(PDF) 716 Page - Freescale Semiconductor, Inc