PC912XDP512F0MPVR datasheet(718/1348 Pages) FREESCALE

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Chapter 19 S12X Debug (S12XDBGV2) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

720

Freescale Semiconductor

19.4.4

State Sequence Control

Figure 19-23. State Sequencer Diagram

The state sequence control allows a deﬁned sequence of events to provide a trigger point for tracing of data

in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register,

then State1 of the state sequencer is entered. Further transitions between the states are then controlled by

the state control registers and depend upon a selected trigger mode condition being met. From ﬁnal state

the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is

not restricted. Each transition updates the SSF[2:0] ﬂags in DBGSR accordingly to indicate the current

state.

Alternatively writing to the TRIG bit in DBGSC1, the ﬁnal state is entered and tracing starts immediately

if the TSOURCE bits are conﬁgured for tracing.

A tag hit through TAGHI/TAGLO causes a breakpoint, if breakpoints are enabled, and ends tracing

immediately independent of the trigger alignment bits TALIGN[1:0].

Furthermore, each comparator channel can be individually conﬁgured to generate an immediate

breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers independent

of the state sequencer state. Thus it is possible to generate an immediate breakpoint on selected channels,

while a state sequencer transition can be initiated by a match on other channels.

An XGATE S/W breakpoint request, if enabled causes a transition to the ﬁnal state and generates a

breakpoint request to the CPU immediately.

If neither tracing nor breakpoints are enabled then, when a forced match triggers to ﬁnal state, it can only

be returned to the disarmed state0 by clearing the ARM bit by software. This also applies to the case that

BDM breakpoints are enabled, but the BDM is disabled. Furthermore if neither tracing nor breakpoints are

enabled, forced triggers on channels with BRK set cause a transition to the state determined by the state

sequencer as if the BRK bit were not being used.

If neither tracing nor breakpoints are enabled then when a tagged match triggers to ﬁnal state, the state

sequencer returns to the disarmed state0.

State1

Final State

State3

ARM = 1

Session complete

(disarm)

State2

State 0

(Disarmed)

ARM = 0

ARM=0

ARM = 0

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