PC912XDP512F0MPVR datasheet(721/1348 Pages) FREESCALE

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Chapter 19 S12X Debug (S12XDBGV2) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

723

Loop1 mode only inhibits consecutive duplicate source address entries that would typically be stored in

most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector

addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG

module is designed to help ﬁnd.

NOTE

In certain very tight loops, the source address will have already been fetched

again before the background comparator is updated. This results in the

source address being stored twice before further duplicate entries are

suppressed. This condition occurs with branch-on-bit instructions when the

branch is fetched by the ﬁrst P-cycle of the branch or with loop-construct

instructions in which the branch is fetched with the ﬁrst or second P cycle.

See examples below:

LOOP

INX

;1-byte instruction fetched by 1st P-cycle of BRCLR

BRCLR

CMPTMP,#$0c,LOOP

;the BRCLR instruction also will be fetched by 1st P-cycle

;of BRCLR

LOOP2

BRN*

; 2-byte instruction fetched by 1st P-cycle of DBNE

NOP

; 1-byte instruction fetched by 2nd P-cycle of DBNE

DBNE

A,LOOP2

; this instruction also fetched by 2nd P-cycle of DBNE

19.4.5.2.3

Detail Mode

In detail mode, address and data for all memory and register accesses is stored in the trace buffer. In the

case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced.

This mode is intended to supply additional information on indexed, indirect addressing modes where

storing only the destination address would not provide all information required for a user to determine

where the code is in error. This mode also features information byte storage to the trace buffer, for each

address byte storage. The information byte indicates the size of access (word or byte), the type of access

(read or write).

When tracing CPU activity in detail mode, all cycles are traced except those when the CPU is either in a

free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide a snapshot

of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity occurring at the

time of the trace buffer entry. When tracing CPU activity alone in detail mode, the address range can be

limited to a range speciﬁed by the TRANGE bits in DBGTCR. This function uses comparators C and D

to deﬁne an address range inside which CPU activity should be traced (see Table 19-10). Thus, the traced

CPU activity can be restricted to register range accesses.

When tracing XGATE activity in detail mode, all cycles apart from opcode fetch and free cycles are stored

to the trace buffer. Additionally the CPU program counter is stored at the time of the XGATE trace buffer

entry to provide a snapshot of CPU activity.

19.4.5.3

Trace Buffer Organization

The buffer can be used to trace either from CPU, from XGATE or from both sources. An “X” preﬁx

denotes information from the XGATE module, a “C” preﬁx denotes information from the CPU.

ADRH,ADRM,ADRL denote address high, middle and low byte respectively. INF bytes contain control

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