PC912XDP512F0MPVR datasheet(753/1348 Pages) FREESCALE

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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

755

20.3.2.4

Debug Control Register2 (DBGC2)

Read: Anytime

Write: Anytime the module is disarmed.

This register conﬁgures the comparators for range matching.

Address: 0x0023

76543210

0000

CDCM

ABCM

Reset

00000000

= Unimplemented or Reserved

Figure 20-6. Debug Control Register2 (DBGC2)

Table 20-13. DBGC2 Field Descriptions

Field

Description

3–2

CDCM[1:0]

C and D Comparator Match Control — These bits determine the C and D comparator match mapping as

described in Table 20-14.

1–0

ABCM[1:0]

A and B Comparator Match Control — These bits determine the A and B comparator match mapping as

described in Table 20-15.

Table 20-14. CDCM Encoding

CDCM

Description

Match2 mapped to comparator C match....... Match3 mapped to comparator D match.

Match2 mapped to comparator C/D inside range....... Match3 disabled.

Match2 mapped to comparator C/D outside range....... Match3 disabled.

Reserved

Table 20-15. ABCM Encoding

ABCM

Description

Match0 mapped to comparator A match....... Match1 mapped to comparator B match.

Match 0 mapped to comparator A/B inside range....... Match1 disabled.

Match 0 mapped to comparator A/B outside range....... Match1 disabled.

Reserved

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