PC912XDP512F0MPVR datasheet(762/1348 Pages) FREESCALE

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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

Table 20-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for

tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the

instruction queue. Thus these bits are ignored if tagged triggering is selected.

BRK

Break — This bit controls whether a comparator match terminates a debug session immediately,

independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be

enabled using the DBGC1 bits DBGBRK[1:0].

0 The debug session termination is dependent upon the state sequencer and trigger conditions.

1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,

tracing, if active, is terminated and the module disarmed.

Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the

associated comparator. The RW bit is not used if RWE = 0.

0 Write cycle will be matched

1 Read cycle will be matched

RWE

Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the

associated comparator. This bit is not useful for tagged operations.

0 Read/Write is not used in comparison

1 Read/Write is used in comparison

SRC

Determines mapping of comparator to S12XCPU or XGATE

0 The comparator is mapped to S12XCPU buses

1 The comparator is mapped to XGATE address and data buses

COMPE

Determines if comparator is enabled

0 The comparator is not enabled

1 The comparator is enabled for state sequence triggers or tag generation

Table 20-28. Read or Write Comparison Logic Table

RWE Bit

RW Bit

RW Signal

Comment

RW not used in comparison

Write data bus

No match

Read data bus

Table 20-27. DBGXCTL Field Descriptions (continued)

Field

Description

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