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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 786 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 786 Page - Freescale Semiconductor, Inc |
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786 / 1348 page  Chapter 21 External Bus Interface (S12XEBIV2) MC9S12XDP512 Data Sheet, Rev. 2.21 788 Freescale Semiconductor 21.1.3 Block Diagram Figure 21-1 is a block diagram of the XEBI with all related I/O signals. Figure 21-1. XEBI Block Diagram 21.2 External Signal Description The user is advised to refer to the SoC section for port configuration and location of external bus signals. NOTE The following external bus related signals are described in other sections: CS2, CS1, CS0 (chip selects) — S12X_MMC section ECLK, ECLKX2 (free-running clocks) — PIM section TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section Table 21-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section and PIM section for reset states of these pins and associated pull-ups or pull-downs. XEBI ADDR[22:0] DATA[15:0] LSTRB R/W UDS LDS RE WE EWAIT ACC[2:0] IQSTAT[3:0] IVD[15:0] |
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