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PC912XDP512F0MPVR 데이터시트(PDF) 782 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 782 Page - Freescale Semiconductor, Inc |
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782 / 1348 page ![]() Chapter 20 S12X Debug (S12XDBGV3) Module MC9S12XDP512 Data Sheet, Rev. 2.21 784 Freescale Semiconductor upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the S12XCPU program flow, but it is necessary to set XGSBPE. Furthermore, if a breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an S12XCPU breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module. 20.4.7.2 Breakpoints From Internal Comparator Channel Final State Triggers Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 20-44). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent of tracing trigger alignment. 20.4.7.3 Breakpoints Generated Via The TRIG Bit If a TRIG triggers occur, the Final State is entered. Tracing trigger alignment is defined by the TALIGN bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 20-44). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if the S12XDBG module is disarmed. Table 20-44. Breakpoint Setup For Both XGATE and S12XCPU Breakpoints BRK TALIGN DBGBRK[n] Breakpoint Alignment 0 00 0 Fill Trace Buffer until trigger (no breakpoints — keep running) 0 00 1 Fill Trace Buffer until trigger, then breakpoint request occurs 0 01 0 Start Trace Buffer at trigger (no breakpoints — keep running) 0 01 1 Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full 0 10 0 Store a further 32 Trace Buffer line entries after trigger (no breakpoints — keep running) 0 10 1 Store a further 32 Trace Buffer line entries after trigger Request breakpoint after the 32 further Trace Buffer entries 1 00,01,10 1 Terminate tracing and generate breakpoint immediately on trigger 1 00,01,10 0 Terminate tracing immediately on trigger x 11 x Reserved |
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