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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 825 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 825 Page - Freescale Semiconductor, Inc |
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825 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 827 22.3.2.1 Port A Data Register (PORTA) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. Write: Anytime. In emulation modes, write operations will also be directed to the external bus. 22.3.2.2 Port B Data Register (PORTB) Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source is depending on the data direction value. 76543210 R PA7PA6 PA5PA4 PA3PA2 PA1PA0 W Alt. Function ADDR15 mux IVD15 ADDR14 mux IVD14 ADDR13 mux IVD13 ADDR12 mux IVD12 ADDR11 mux IVD11 ADDR10 mux IVD10 ADDR9 mux IVD9 ADDR8 mux IVD8 Reset 00000000 Figure 22-3. Port A Data Register (PORTA) Table 22-4. PORTA Field Descriptions Field Description 7–0 PA[7:0] Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in expanded modes. When this port is not used for external addresses, these pins can be used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register, otherwise the buffered pin input state is read. 76543210 R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W Alt. Function ADDR7 mux IVD7 ADDR6 mux IVD6 ADDR5 mux IVD5 ADDR4 mux IVD4 ADDR3 mux IVD3 ADDR2 mux IVD2 ADDR1 mux IVD1 ADDR0 mux IVD0 or UDS Reset 00000000 Figure 22-4. Port B Data Register (PORTB) |
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