PC912XDP512F0MPVR datasheet(827/1348 Pages) FREESCALE

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

829

22.3.2.3

Port A Data Direction Register (DDRA)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

22.3.2.4

Port B Data Direction Register (DDRB)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other

modes the data are read from this register.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

76543210

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Reset

00000000

Figure 22-5. Port A Data Direction Register (DDRA)

Table 22-6. DDRA Field Descriptions

Field

Description

7–0

DDRA[7:0]

Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general

purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTA after changing the DDRA register.

76543210

DDRB7

DDRB6

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Reset

00000000

Figure 22-6. Port B Data Direction Register (DDRB)

Table 22-7. DDRB Field Descriptions

Field

Description

7–0

DDRB[7:0]

Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general

purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTB after changing the DDRB register.

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