PC912XDP512F0MPVR datasheet(853/1348 Pages) FREESCALE

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

855

22.3.2.38 Port P Data Register (PTP)

Read: Anytime.

Write: Anytime.

Port P pins 7, and 5–0 are associated with the PWM as well as the SPI1 and SPI2 modules. These pins can

be used as general purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

The PWM function takes precedence over the general purpose I/O and the SPI2 or SPI1 function if the

associated PWM channel is enabled. While channels 6 and 5-0 are output only if the respective channel is

enabled, channel 7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM section

for details.

The SPI2 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section

for details.

The SPI1 function takes precedence over the general purpose I/O function if enabled. Refer to SPI section

for details.

76543210

PTP7

PTP6

PTP5

PTP4

PTP3

PTP2

PTP1

PTP0

PWM

PWM7

PWM6

PWM5

PWM4

PWM3

PWM2

PWM1

PWM0

SPI

SCK2

SS2

MOSI2

MISO2

SS1

SCK1

MOSI1

MISO1

Reset

00000000

Figure 22-40. Port P Data Register (PTP)

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