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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PC912XDP512F0MPVR 데이터시트(PDF) 857 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 857 Page - Freescale Semiconductor, Inc |
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857 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 859 22.3.2.43 Port P Polarity Select Register (PPSP) Read: Anytime. Write: Anytime. This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 22.3.2.44 Port P Interrupt Enable Register (PIEP) Read: Anytime. Write: Anytime. This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P. 76543210 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 00000000 Figure 22-45. Port P Polarity Select Register (PPSP) Table 22-42. PPSP Field Descriptions Field Description 7–0 PPSP[7:0] Polarity Select Port P 0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-up device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register.A pull-down device is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used as input. 76543210 R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W Reset 00000000 Figure 22-46. Port P Interrupt Enable Register (PIEP) Table 22-43. PIEP Field Descriptions Field Description 7–0 PIEP[7:0] Interrupt Enable Port P 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. |
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