PC912XDP512F0MPVR datasheet(861/1348 Pages) FREESCALE

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

863

22.3.2.48 Port H Data Direction Register (DDRH)

Read: Anytime.

Write: Anytime.

This register configures each port H pin as either input or output.

If the associated SCI channel or routed SPI module is enabled this register has no effect on the pins.

The SCI forces the I/O state to be an output for each port line associated with an enabled output (TXD5,

TXD4). It also forces the I/O state to be an input for each port line associated with an enabled input (RXD5,

RXD4). In those cases the data direction bits will not change.

If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are

disabled.

76543210

DDRH7

DDRH6

DDRH5

DDRH4

DDRH3

DDRH2

DDRH1

DDRH0

Reset

00000000

Figure 22-50. Port H Data Direction Register (DDRH)

Table 22-45. DDRH Field Descriptions

Field

Description

7–0

DDRH[7:0]

Data Direction Port H

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTH or PTIH registers, when changing the DDRH register.

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