PC912XDP512F0MPVR datasheet(919/1348 Pages) FREESCALE

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23.0.5.2

Port B Data Register (PORTB)

Read: Anytime.

Write: Anytime.

23.0.5.3

Port A Data Direction Register (DDRA)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in

all other modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 23-4. PORTA Field Descriptions

Field

Description

7–0

PA[7:0]

Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively inexpanded

modesWhen this port is not used for external addresses, these pins can be used as general purpose I/O. If the

data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,

otherwise the buffered pin input state is read.

76543210

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

Reset

00000000

Figure 23-4. Port B Data Register (PORTB)

Table 23-5. PORTB Field Descriptions

Field

Description

7–0

PB[7:0]

Port B — Port B pins 7–0 are associated with address outputs ADDR7 through ADDR1 respectively in expanded

modes. Pin 0 is associated with output ADDR0 in emulation modes and special test mode and with Upper Data

Select (UDS) in normal expanded mode. When this port is not used for external addresses, these pins can be

used as general purpose I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read

returns the value of the port register, otherwise the buffered pin input state is read.

76543210

DDRA7

DDRA6

DDRA5

DDRA4

DDRA3

DDRA2

DDRA1

DDRA0

Reset

00000000

Figure 23-5. Port A Data Direction Register (DDRA)

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