PC912XDP512F0MPVR datasheet(923/1348 Pages) FREESCALE

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23.0.5.10 Port E Data Direction Register (DDRE)

Read: Anytime. In emulation modes, read operations will return the data from the external bus, in

all other modes the data source is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Table 23-12. PORTE Field Descriptions

Field

Description

7–0

PE[7:0]

Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include

mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI,

TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.

When not used for any of these speciﬁc functions, Port E pins 7–2 can be used as general purpose I/O and

pins 1–0 can be used as general purpose inputs.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port

Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.

Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.

76543210

DDRE7

DDRE6

DDRE5

DDRE4

DDRE3

DDRE2

Reset

00000000

= Unimplemented or Reserved

Figure 23-12. Port E Data Direction Register (DDRE)

Table 23-13. DDRE Field Descriptions

Field

Description

7–0

DDRE[7:2]

Data Direction Port E — his register controls the data direction for port E. When Port E is operating as a general

purpose I/O port, DDRE determines whether each pin is an input or output. A logic level “1” causes the

associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.

Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be conﬁgured as outputs. Port E, bits

1 and 0, can be read regardless of whether the alternate interrupt function is enabled.

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PORTE after changing the DDRE register.

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