PC912XDP512F0MPVR datasheet(932/1348 Pages) FREESCALE

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

934

Freescale Semiconductor

23.0.5.23 Port S Data Register (PTS)

Read: Anytime.

Write: Anytime.

Port S pins 7–4 are associated with the SPI0. The SPI0 pin configuration is determined by several status

bits in the SPI0 module. Refer to SPI section for details. When not used with the SPI0, these pins can be

used as general purpose I/O.

Port S bits 3–0 are associated with the SCI1 and SCI0. The SCI ports associated with transmit pins 3 and

1 are configured as outputs if the transmitter is enabled. The SCI ports associated with receive pins 2 and

0 are configured as inputs if the receiver is enabled. Refer to SCI section for details. When not used with

the SCI, these pins can be used as general purpose I/O.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the

port register, otherwise the buffered pin input state is read.

23.0.5.24 Port S Input Register (PTIS)

Table 23-26. PPST Field Descriptions

Field

Description

7–0

PPST[7:0]

Pull Select Port T

0 A pull-up device is connected to the associated port T pin, if enabled by the associated bit in register PERT

and if the port is used as input.

1 A pull-down device is connected to the associated port T pin, if enabled by the associated bit in register PERT

and if the port is used as input.

76543210

PTS7

PTS6

PTS5

PTS4

PTS3

PTS2

PTS1

PTS0

SCI/SPI

SS0

SCK0

MOSI0

MISO0

TXD1

RXD1

TXD0

RXD0

Reset

00000000

Figure 23-25. Port S Data Register (PTS)

76543210

PTIS7

PTIS6

PTIS5

PTIS4

PTIS3

PTIS2

PTIS1

PTIS0

Reset1

1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the

associated pin values.

————————

= Unimplemented or Reserved

Figure 23-26. Port S Input Register (PTIS)

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