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PC912XDP512F0MPVR 데이터시트(PDF) 933 Page - Freescale Semiconductor, Inc

부품명 PC912XDP512F0MPVR
상세설명  HCS12X Microcontrollers
PDF  1348 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 933 Page - Freescale Semiconductor, Inc

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Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This also can be used to
detect overload or short circuit conditions on output pins.
23.0.5.25 Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
23.0.5.26 Port S Reduced Drive Register (RDRS)
Read: Anytime.
Write: Anytime.
76543210
R
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
W
Reset
00000000
Figure 23-27. Port S Data Direction Register (DDRS)
Table 23-27. DDRS Field Descriptions
Field
Description
7–0
DDRS[7:0]
Data Direction Port S
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTS or PTIS registers, when changing the DDRS register.
76543210
R
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
W
Reset
00000000
Figure 23-28. Port S Reduced Drive Register (RDRS)



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