PC912XDP512F0MPVR datasheet(944/1348 Pages) FREESCALE

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

946

Freescale Semiconductor

23.0.5.44 Port P Interrupt Enable Register (PIEP)

Read: Anytime.

Write: Anytime.

This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with

Port P.

23.0.5.45 Port P Interrupt Flag Register (PIFP)

Read: Anytime.

Write: Anytime.

Table 23-42. PPSP Field Descriptions

Field

Description

7–0

PPSP[7:0]

Polarity Select Port P

0 Falling edge on the associated port P pin sets the associated ﬂag bit in the PIFP register.A pull-up device is

connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used

as input.

1 Rising edge on the associated port P pin sets the associated ﬂag bit in the PIFP register.A pull-down device

is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is

used as input.

76543210

PIEP7

PIEP6

PIEP5

PIEP4

PIEP3

PIEP2

PIEP1

PIEP0

Reset

00000000

Figure 23-46. Port P Interrupt Enable Register (PIEP)

Table 23-43. PIEP Field Descriptions

Field

Description

7–0

PIEP[7:0]

Interrupt Enable Port P

0 Interrupt is disabled (interrupt ﬂag masked).

1 Interrupt is enabled.

76543210

PIFP7

PIFP6

PIFP5

PIFP4

PIFP3

PIFP2

PIFP1

PIFP0

Reset

00000000

Figure 23-47. Port P Interrupt Flag Register (PIFP)

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