PC912XDP512F0MPVR datasheet(945/1348 Pages) FREESCALE

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Each flag is set by an active edge on the associated input pin. This could be a rising or a falling

edge based on the state of the PPSP register. To clear this flag, write logic level “1” to the

corresponding bit in the PIFP register. Writing a “0” has no effect.

23.0.5.46 Port H Data Register (PTH)

Read: Anytime.

Write: Anytime.

Port H pins 7–0 are associated with the SCI4 as well as the routed SPI1 and SPI2.

These pins can be used as general purpose I/O when not used with any of the peripherals.

If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value

of the port register, otherwise the buffered pin input state is read.

The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if

the routed SPI2 module is enabled. Refer to SPI section for details.The routed SPI1 function takes

precedence over the general purpose I/O function if the routed SPI1 is enabled. Refer to SPI section

for details.

The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled

Table 23-44. PIFP Field Descriptions

Field

Description

7–0

PIFP[7:0]

Interrupt Flags Port P

0 No active edge pending. Writing a “0” has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

Writing a logic level “1” clears the associated ﬂag.

76543210

PTH7

PTH6

PTH5

PTH4

PTH3

PTH2

PTH1

PTH0

SCI

TXD4

RXD4

Routed

SPI

SS2

SCK2

MOSI2

MISO2

SS1

SCK1

MOSI1

MISO1

Reset

00000000

Figure 23-48. Port H Data Register (PTH)

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