PC912XDP512F0MPVR datasheet(1020/1348 Pages) FREESCALE

1020 / 1348 page

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1022

Freescale Semiconductor

24.0.5.53 Port J Reduced Drive Register (RDRJ)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port J output pin as either full or reduced. If the port is

used as input this bit is ignored.

24.0.5.54 Port J Pull Device Enable Register (PERJ)

Read: Anytime.

Write: Anytime.

This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or

as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up

device is enabled.

76543210

RDRJ7

RDRJ6

0000

RDRJ1

RDRJ0

Reset

00000000

= Unimplemented or Reserved

Figure 24-55. Port J Reduced Drive Register (RDRJ)

Table 24-49. RDRJ Field Descriptions

Field

Description

7–0

RDRJ[7:6]

RDRJ[1:0]

Reduced Drive Port J

0 Full drive strength at output.

1 Associated pin drives at about 1/6 of the full drive strength.

76543210

PERJ7

PERJ6

0000

PERJ1

PERJ0

Reset

11000011

= Unimplemented or Reserved

Figure 24-56. Port J Pull Device Enable Register (PERJ)

PC912XDP512F0MPVR 데이터시트(PDF) 1020 Page - Freescale Semiconductor, Inc

PC912XDP512F0MPVR 데이터시트(HTML) 1020 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL