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PC912XDP512F0MPVR 데이터시트(PDF) 1017 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0MPVR 데이터시트(HTML) 1017 Page - Freescale Semiconductor, Inc |
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1017 / 1348 page ![]() 24.0.5.48 Port H Interrupt Enable Register (PIEH) Read: Anytime. Write: Anytime. This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H. 24.0.5.49 Port H Interrupt Flag Register (PIFH) Read: Anytime. Write: Anytime. Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the state of the PPSH register. To clear this flag, write logic level “1” to the corresponding bit in the PIFH register. Writing a “0” has no effect. Table 24-44. PPSH Field Descriptions Field Description 7–0 PPSH[7:0] Polarity Select Port H 0 Falling edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-up device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 1 Rising edge on the associated port H pin sets the associated flag bit in the PIFH register. A pull-down device is connected to the associated port H pin, if enabled by the associated bit in register PERH and if the port is used as input. 76543210 R PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 W Reset 00000000 Figure 24-50. Port H Interrupt Enable Register (PIEH) Table 24-45. PIEH Field Descriptions Field Description 7–0 PIEH[7:0] Interrupt Enable Port H 0 Interrupt is disabled (interrupt flag masked). 1 Interrupt is enabled. 76543210 R PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 W Reset 00000000 Figure 24-51. Port H Interrupt Flag Register (PIFH) |
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