PC912XDP512F0MPVR datasheet(1131/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1133

27.4.2.2

Data Compress Command

The data compress operation will check Flash code integrity by compressing data from a selected portion

of the Flash memory into a signature analyzer.

An example ﬂow to execute the data compress operation is shown in Figure 27-26. The data compress

command write sequence is as follows:

1. Write to a Flash block address to start the command write sequence for the data compress

command. The address written determines the starting address for the data compress operation and

the data written determines the number of consecutive words to compress. If the data value written

is 0x0000, 64K addresses or 128 Kbytes will be compressed. Multiple Flash blocks can be

simultaneously compressed by writing to the same relative address in each Flash block. If more

than one Flash block is written to in this step, the ﬁrst data written will determine the number of

consecutive words to compress in each selected Flash block.

2. Write the data compress command, 0x06, to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the data compress

command.

After launching the data compress command, the CCIF ﬂag in the FSTAT register will set after the data

compress operation has completed. The number of bus cycles required to execute the data compress

operation is equal to two times the number of consecutive words to compress plus the number of Flash

blocks simultaneously compressed plus 18 bus cycles as measured from the time the CBEIF ﬂag is cleared

until the CCIF ﬂag is set. Once the CCIF ﬂag is set, the signature generated by the data compress operation

is available in the FDATA registers. The signature in the FDATA registers can be compared to the expected

signature to determine the integrity of the selected data stored in the selected Flash memory. If the last

address of a Flash block is reached during the data compress operation, data compression will continue

with the starting address of the same Flash block. The MRDS bits in the FTSTMOD register will determine

the sense-amp margin setting during the data compress operation.

NOTE

Since the FDATA registers (or data buffer) are written to as part of the data

compress operation, a command write sequence is not allowed to be

buffered behind a data compress command write sequence. The CBEIF ﬂag

will not set after launching the data compress command to indicate that a

command should not be buffered behind it. If an attempt is made to start a

new command write sequence with a data compress operation active, the

ACCERR ﬂag in the FSTAT register will be set. A new command write

sequence should only be started after reading the signature stored in the

FDATA registers.

In order to take corrective action, it is recommended that the data compress command be executed on a

Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid

signature, the Flash sector should be erased using the sector erase command and then reprogrammed using

the program command.

The data compress command can be used to verify that a sector or sequential set of sectors are erased.

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