PC912XDP512F0MPVR datasheet(1127/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1129

27.4.1.2

Command Write Sequence

The Flash command controller is used to supervise the command write sequence to execute program,

erase, erase verify, erase abort, and data compress algorithms.

Before starting a command write sequence, the ACCERR and PVIOL ﬂags in the FSTAT register must be

clear (see Section 27.3.2.6, “Flash Status Register (FSTAT)”) and the CBEIF ﬂag should be tested to

determine the state of the address, data and command buffers. If the CBEIF ﬂag is set, indicating the

buffers are empty, a new command write sequence can be started. If the CBEIF ﬂag is clear, indicating the

buffers are not available, a new command write sequence will overwrite the contents of the address, data

and command buffers.

A command write sequence consists of three steps which must be strictly adhered to with writes to the

Flash module not permitted between the steps. However, Flash register and array reads are allowed during

a command write sequence. The basic command write sequence is as follows:

1. Write to a valid address in the Flash memory. Addresses in multiple Flash blocks can be written to

as long as the location is at the same relative address in each available Flash block. Multiple

addresses must be written in Flash block order starting with the lower Flash block.

2. Write a valid command to the FCMD register.

3. Clear the CBEIF ﬂag in the FSTAT register by writing a 1 to CBEIF to launch the command.

The address written in step 1 will be stored in the FADDR registers and the data will be stored in the

FDATA registers. If the CBEIF ﬂag in the FSTAT register is clear when the ﬁrst Flash array write occurs,

the contents of the address and data buffers will be overwritten and the CBEIF ﬂag will be set. When the

CBEIF ﬂag is cleared, the CCIF ﬂag is cleared on the same bus cycle by the Flash command controller

indicating that the command was successfully launched. For all command write sequences except data

compress and sector erase abort, the CBEIF ﬂag will set four bus cycles after the CCIF ﬂag is cleared

indicating that the address, data, and command buffers are ready for a new command write sequence to

begin. For data compress and sector erase abort operations, the CBEIF ﬂag will remain clear until the

operation completes. Except for the sector erase abort command, a buffered command will wait for the

active operation to be completed before being launched. The sector erase abort command is launched when

the CBEIF ﬂag is cleared as part of a sector erase abort command write sequence. Once a command is

launched, the completion of the command operation is indicated by the setting of the CCIF ﬂag in the

FSTAT register. The CCIF ﬂag will set upon completion of all active and buffered commands.

27.4.2

Flash Commands

Table 27-20 summarizes the valid Flash commands along with the effects of the commands on the Flash

block.

Table 27-20. Flash Command Description

FCMDB

NVM

Command

Function on Flash Memory

0x05

Erase

Verify

Verify all memory bytes in the Flash block are erased.

If the Flash block is erased, the BLANK ﬂag in the FSTAT register will set upon command

completion.

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