PC912XDP512F0MPVR datasheet(1142/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

1144

Freescale Semiconductor

27.4.3

Illegal Flash Operations

The ACCERR ﬂag will be set during the command write sequence if any of the following illegal steps are

performed, causing the command write sequence to immediately abort:

1. Writing to a Flash address before initializing the FCLKDIV register.

2. Writing a byte or misaligned word to a valid Flash address.

3. Starting a command write sequence while a data compress operation is active.

4. Starting a command write sequence while a sector erase abort operation is active.

5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address

as the ﬁrst one written in the same command write sequence.

6. Writing to any Flash register other than FCMD after writing to a Flash address.

7. Writing a second command to the FCMD register in the same command write sequence.

8. Writing an invalid command to the FCMD register.

9. When security is enabled, writing a command other than mass erase to the FCMD register when

the write originates from a non-secure memory location or from the Background Debug Mode.

10. Writing to a Flash address after writing to the FCMD register.

11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD

12. Writing a 0 to the CBEIF ﬂag in the FSTAT register to abort a command write sequence.

The ACCERR ﬂag will not be set if any Flash register is read during a valid command write sequence.

The ACCERR ﬂag will also be set if any of the following events occur:

1. Launching the sector erase abort command while a sector erase operation is active which results in

the early termination of the sector erase operation (see Section 27.4.2.6, “Sector Erase Abort

Command”).

2. The MCU enters stop mode and a program or erase operation is in progress. The operation is

aborted immediately and any pending command is purged (see Section 27.5.2, “Stop Mode”).

If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return

invalid data and the ACCERR ﬂag will not be set.

If the ACCERR ﬂag is set in the FSTAT register, the user must clear the ACCERR ﬂag before starting

another command write sequence (see Section 27.3.2.6, “Flash Status Register (FSTAT)”).

The PVIOL ﬂag will be set after the command is written to the FCMD register during a command write

sequence if any of the following illegal operations are attempted, causing the command write sequence to

immediately abort:

1. Writing the program command if an address written in the command write sequence was in a

protected area of the Flash memory

2. Writing the sector erase command if an address written in the command write sequence was in a

protected area of the Flash memory

3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the

block

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