PC912XDP512F0MPVR datasheet(1145/1348 Pages) FREESCALE

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Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1147

unaffected by the backdoor key access sequence. After the next reset of the MCU, the security state of the

Flash module is determined by the Flash security byte (0x7F_FF0F). The backdoor key access sequence

has no effect on the program and erase protections deﬁned in the Flash protection register.

It is not possible to unsecure the MCU in special single chip mode by using the backdoor key access

sequence in background debug mode (BDM).

27.6.2

Unsecuring the MCU in Special Single Chip Mode using BDM

The MCU can be unsecured in special single chip mode by erasing the Flash module by the following

method:

•

Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM

secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass

erase command write sequence to erase the Flash memory.

After the CCIF ﬂag sets to indicate that the mass operation has completed, reset the MCU into special

single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the

UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security

state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte

may be programmed to the unsecure state by the following method:

•

Send BDM commands to execute a word program sequence to program the Flash security byte to

the unsecured state and reset the MCU.

27.7

Resets

27.7.1

Flash Reset Sequence

On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following

registers from the Flash memory according to Table 27-1:

•

FPROT — Flash Protection Register (see Section 27.3.2.5).

•

FCTL - Flash Control Register (see Section 27.3.2.8).

•

FSEC — Flash Security Register (see Section 27.3.2.2).

27.7.2

Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

27.8

Interrupts

The Flash module can generate an interrupt when all Flash command operations have completed, when the

Flash address, data and command buffers are empty.

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