PC912XDP512F0MPVR datasheet(117/1348 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

117

2.6.2

PLL Lock Interrupt

The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from

a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the

LOCKIE bit to 0. The PLL Lock interrupt ﬂag (LOCKIF) is set to1 when the LOCK condition has

changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.

2.6.3

Self Clock Mode Interrupt

The CRG generates a self clock mode interrupt when the SCM condition of the system has changed, either

entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit

(SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on reset (POR)

or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details

on the clock quality check refer to Section 2.4.1.4, “Clock Quality Checker”. If the clock monitor is

enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).

SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt ﬂag (SCMIF) is set

to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.

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