PC912XDP512F0MPVR datasheet(1196/1348 Pages) FREESCALE

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Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)

MC9S12XDP512 Data Sheet, Rev. 2.21

1198

Freescale Semiconductor

MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.

29.3.2.4

Flash Conﬁguration Register (FCNFG)

The FCNFG register enables the Flash interrupts and gates the security backdoor writes.

CBEIE, CCIE and KEYACC bits are readable and writable while all remaining bits read 0 and are not

writable in normal mode. KEYACC is only writable if KEYEN (see Section 29.3.2.2, “Flash Security

76543210

MRDS

00000

Reset

00000000

= Unimplemented or Reserved

Figure 29-6. Flash Test Mode Register (FTSTMOD)

Table 29-6. FTSTMOD Field Descriptions

Field

Description

6:5

MRDS[1:0]

Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash

array as shown in Table 29-7.

Table 29-7. FTSTMOD Margin Read Settings

MRDS[1:0]

Margin Read Setting

Normal

Program Margin1

1 Flash array reads will be sensitive to program margin.

Erase Margin2

2 Flash array reads will be sensitive to erase margin.

Normal

76543210

CBEIE

CCIE

KEYACC

Undeﬁned

0000

Reset

Undeﬁned

0000

= Unimplemented or Reserved

Figure 29-7. Flash Conﬁguration Register (FCNFG)

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