PC912XDP512F0MPVR datasheet(1235/1348 Pages) FREESCALE

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Chapter 30 Security (S12X9SECV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

1237

Special single chip erase and unsecure sequence:

1. Reset into special single chip mode.

2. Write an appropriate value to the ECLKDIV register for correct timing.

3. Write 0xFF to the EPROT register to disable protection.

4. Write 0x30 to the ESTAT register to clear the PVIOL and ACCERR bits.

5. Write 0x0000 to the EDATA register (0x011A–0x011B).

6. Write 0x0000 to the EADDR register (0x0118–0x0119).

7. Write 0x41 (mass erase) to the ECMD register.

8. Write 0x80 to the ESTAT register to clear CBEIF.

9. Write an appropriate value to the FCLKDIV register for correct timing.

10. Write 0x00 to the FCNFG register to select Flash block 0.

11. Write 0x10 to the FTSTMOD register (0x0102) to set the WRALL bit, so the following writes

affect all Flash blocks.

12. Write 0xFF to the FPROT register to disable protection.

13. Write 0x30 to the FSTAT register to clear the PVIOL and ACCERR bits.

14. Write 0x0000 to the FDATA register (0x010A–0x010B).

15. Write 0x0000 to the FADDR register (0x0108–0x0109).

16. Write 0x41 (mass erase) to the FCMD register.

17. Write 0x80 to the FSTAT register to clear CBEIF.

18. Wait until all CCIF ﬂags are set.

19. Reset back into special single chip mode.

20. Write an appropriate value to the FCLKDIV register for correct timing.

21. Write 0x00 to the FCNFG register to select Flash block 0.

22. Write 0xFF to the FPROT register to disable protection.

23. Write 0xFFBE to Flash address 0xFF0E.

24. Write 0x20 (program) to the FCMD register.

25. Write 0x80 to the FSTAT register to clear CBEIF.

26. Wait until the CCIF ﬂag in FSTAT is are set.

27. Reset into any mode.

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