ATSAM3U datasheet(60/62 Pages) ATMEL

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6430CS–ATARM–09-Apr-10

SAM3U Series

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6430BS

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Introduction:

Section 1. ”SAM3U Description”, Updated: 52 Kbytes of SRAM. 4x USARTs (SAM3U1C/2C/4C have 3), up to

2x TWIs (SAM3U1C/2C/4C have 1), up to 5x SPIs SAM3U1C/2C/4C have 4),

Table 1-1, “Configuration Summary”,EBI column updated, 8 bits for SAM3U1C/2C/4C

SAM3U4/3/2C rows FWUP replaces NO in FWUP,SHDN pins column

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Figure 2-1 ”144-pin SAM3U4/2/1E Block Diagram” and Figure 2-2 ”100-pin SAM3U4/2/1C Block Diagram”

updated, SM cell removed; UART moved to peripheral area, added Flash Unique block, removed 12B from

ADC block, added SysTick counter and Fmax 96 MHz to M3 block. FWUP replaces WKUP in fig 2-1, FWUP

added to fig 2-2

Figure 2-2 ”100-pin SAM3U4/2/1C Block Diagram”, NWR1/NBS1, NXRP0, A0 removed from block diagram.

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Table 3-1, “Signal Description List”, Schmitt Trigger added ”PIO Controller - PIOA - PIOB - PIOC”. exception

details given in footnote.

VDDIN, VDDOUT added to table.

”Serial Wire/JTAG Debug Port (SWJ-DP)” replaced ICE and JTAG. This section of the table updated

status of pulldowns and pullups specified.

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Section 4. ”Package and Pinout”, reorganized according to product.

Section 4.1 ”SAM3U4/2/1E Package and Pinout” and Section 4.2 ”SAM3U4/2/1C Package and Pinout”,

pinouts finalized in datasheet.

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Section 5.5.1 ”Backup Mode”, BOD replaced by Supply Monitor/SM. FWUP

→Falling Edge Detector.

Figure 5-4 ”Wake-up Source”, BODEN replaced by SMEN.

Table 5-1, “Low Power Mode Configuration Summary”, PIO state in Low Power Modes, backup mode is;

“Previous state saved.

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Section 6.6 ”NRSTB Pin”, VDDIO changed to VDDBU

Section 6. ”Input/Output Lines”, replaces Section 5.8 “Programmable I/O Lines”.

Section 6.1 ”General Purpose I/O Lines (GPIO)” and Section 6.2 ”System I/O Lines”, replace Section 6. “I/O

Line Considerations”.

Figure 6-1 ”On-Die Termination schematic”, added.

Section 6.8 “PIO Controllers”, removed.

Section 8. ”Product Mapping”, title changed from “Memories”.

Section 9. ”Memories”, now comprises Section 9.1 ”Embedded Memories” and Section 9.2 ”External

Memories”.

Section 9.1.3.5 ”Security Bit Feature”, updated

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Table 7-3, “SAM3U Master to Slave Access”, Slave 9, High Speed Peripheral Bridge line added.

Section 7.2 ”APB/AHB Bridges”, reference to ADC updated “10-bit ADC, 12-bit ADC (ADC12B)”.

Table 11-3, “Multiplexing on PIO Controller B (PIOB)”, ADC12B2, ADC12B3 properly listed.

Section 12.10.1 ”12-bit High Speed ADC”, Section 12.10.2 ”10-bit Low Power ADC”, titles changed.

“Quadrature Decoder Logic” on page 51, properly stated in list of TC functions.

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Section 12.10.1 ”12-bit High Speed ADC”, 2nd item on list updated.

Section 12.10.2 ”10-bit Low Power ADC”, Ksample values updated on 2nd item of list.

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