CS1500

DS849A7

13

Jul ?$shortyear>

CONFIDENTIAL

4.1.2

PFC Input Filter Capacitor

To achieve unity power factor, a DCM PFC circuit needs an

input filtering circuit to bypass the high-frequency current so

that the input current consists of the low-frequency portion

only. There are two main factors on PFC input filter capacitor

selection: its voltage ripple and phase lag, which both will

worsen power factor. The filtering capacitance is proportional

Use 0.47

μF for tolerance.

If a PI filter used for suppression of conducted EMI is located

to be moved to the second capacitor.

4.1.3

PFC Boost Inductor

The value of the inductor in normal mode can be calculated by

the following equation, with

α = 0.9 as a derating factor to

ensure the inductor is sized to guarantee DCM operation and

provide a slightly higher power than required by the load:

Choose a 360

μH inductor.

The inductor should be designed so that its saturation current

meets the following requirement, where 0.001126 is a pre-

defined threshold for the current protection algorithm:

where L is the inductance in Henrys.

4.1.4

PFC MOSFET

In normal mode, the PFC MOSFET peak current is equal to

the peak current in the PFC boost inductor:

4.1.5

PFC Diode

The PFC diode peak current in normal mode is the equal to the

inductor peak current:

The PFC Diode average current is calculated as follows:

4.1.6

PFC Output Capacitor

The value of the output capacitor is determined by several

requirements. It must meet the voltage ripple and hold-up time

requirements and the RMS current in the capacitor should not

exceed its RMS current rating.

The following equation defines the size of the output capacitor

to meet the output voltage ripple requirements:

is the output voltage ripple requirement in volts peak-to-peak.

The equation will provide the value of the output capacitor

needed to meet the ripple requirement.

For 10 V of ripple and minimum line frequency of 45 Hz, the

equation becomes:

A second requirement that the output capacitor may be

required to meet is hold-up time. The value of the capacitor

C

1

3.3

nF

W

-------

×

≥

C

1

3.3

120

×

≥

C

1

390nF

≥

0.39

μF

=

[Eq.10]

L

B

αη

V

in min

()

()

×

2

×

V

link

V

in min

()

2

×

()

–

2f

max

V

link

×

×

×

---------------------------------------------------------

×

=

L

B

0.9

0.95

×

90

2

×

400

90

2

×

()

–

270

10

3

×

()

×

90

×

400

×

-------------------------------------------------------------------

×

=

L

B

374

μH

=

[Eq.11]

I

LB pk

()

4P

o

×

αη

×

V

×

in min

()

2

×

------------------------------------------------------

=

I

LB pk

()

3.3A

=

I

LB pk

()

490

×

0.9

0.95

×

90

×

2

×

-----------------------------------------------------

=

[Eq.12]

I

sat

0.001126

L

-------------------------

≤

[Eq.13]

I

FET pk

()

I

LB pk

()

=

I

FET pk

()

3.3A

=

[Eq.14]

I

Dpk

()

I

LB pk

()

=

I

Dpk

()

3.3A

=

[Eq.15]

I

Davg

()

V

link

------------

=

I

Davg

()

0.225A

=

I

Davg

()

90

400

----------

=

[Eq.16]

[Eq.17]

C

out rip

()

P

O

2

π f

line min

()

×

V

link

×ΔV

link rip

()

×

---------------------------------------------------------------------------------------

=

C

out rip

()

90

2

π 45

×

400

×

10

×

-------------------------------------------------

80

==