PLL FREQUENCY SYNTHESIZER FOR PAGER

S5T8809

9

•

Ex 1) FRC = 0, In case of 13bits Program, Fosc = 12.8MHz and 1/8 prescaler is used

[(Osc. Freq. / Prescaler) / Ref. Freq.] = [(12.8MHz / 8) / 6.25kHz] = 256

•

Ex 2) FRC = 1, In case of 15bits Program, Fosc = 12.8MHz and 1/8 prescaler is used

[Osc. Freq. / Ref. Freq.] = [12.8MHz / 6.25kHz] = 2048

NOTE: The PMC bit is Program Mode Control Bit, if [1], the R-Counter will be Enabled

Figure 3. The architecture of R-Count Divider

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

1

MSB

LSB

2

12

2

0

R - counter 13 - bits

PMC bit

TEST1

FRC

LDC

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

MSB

LSB

2

12

2

0

R - counter 15 - bits

PMC bit

TEST1

FRC

LDC

0

0

2

14

12.8MHz

X-Tal

OSCI

1 / 8

Prescaler

FRC

13/15 bits

Counter

12.8MHz

1.6MHz

D0 ------------- D13

Fr

6.25kHz