AT90PWM3 datasheet(36/361 Pages) ATMEL

36 / 361 page

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Figure 7-5.

PCK Clocking System AT90PWM2B/3B

7.6.2

PLL Control and Status Register – PLLCSR

• Bit 7..3 – Res: Reserved Bits

These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero.

• Bit 2 – PLLF: PLL Factor

The PLLF bit is used to select the division factor of the PLL.

If PLLF is set, the PLL output is 64Mhz.

If PLLF is clear, the PLL output is 32Mhz.

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is

started as PLL reference clock. If PLL is selected as a system clock source the value for this bit

is always 1.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable

CLKPLL for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.

7.7

128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25

°C. This clock is used by the Watchdog Oscillator.

7.8

External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

7-6. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

8 MHz

RC OSCILLATOR

OSCCAL

XTAL1

XTAL2

OSCILLATORS

DIVIDE

BY 8

DIVIDE

BY 2

PLL

64x

PLLE

Lock

Detector

PLOCK

SOURCE

PLLF

DIVIDE

BY 4

CLK

PLL

CKSEL3..0

Bit

6543

210

$29 ($29)

–

––––

PLLF

PLLE

PLOCK

PLLCSR

Read/Write

RRR

R/W

Initial Value

0000

0/1

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