AT90PWM3 datasheet(46/361 Pages) ATMEL

46 / 361 page

4317J–AVR–08/10

AT90PWM2/3/2B/3B

Figure 9-1.

Reset Logic

Notes:

1. Values are guidelines only..

2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)

9.0.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 9-1. The POR is activated whenever V

CC is below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V

CC rise. The RESET signal is activated again, without any delay,

when V

CC decreases below the detection level.

Table 9-1.

Reset Characteristics

(1)

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

VPOT

Power-on Reset Threshold

Voltage (rising)

1.4

2.3

Power-on Reset Threshold

Voltage (falling)(2)

1.3

2.3

VRST

RESET Pin Threshold Voltage

0.2Vcc

0.85Vcc

tRST

Minimum pulse width on RESET

400

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

Spike

Filter

Pull-up Resistor

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

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