AD9550

Rev. 0 | Page 15 of 20

DESCRIPTION OF FUNCTIONAL BLOCKS

Input Frequency Prescaler (Divide-by-5)

The divide-by-5 prescaler provides the option to reduce the

input reference frequency by a factor of five. Note that the pre-

scaler physically precedes the ×2 frequency multiplier. This

allows the prescaler to bring a high frequency reference clock

down to a frequency that is within the range of the ×2 frequency

multiplier.

Input ×2 Frequency Multiplier

The ×2 frequency multiplier doubles the frequency at its input,

thereby taking advantage of a higher frequency at the input to

the PLL. This provides greater separation between the frequency

generated by the PLL and the modulation spur associated with

frequency at the PLL input.

PLL (PFD, Charge Pump, VCO, Feedback Divider)

The PLL (see Figure 23) consists of a phase/frequency detector

(PFD), a partially integrated analog loop filter (see Figure 24),

an integrated voltage controlled oscillator (VCO), and a 20-bit

programmable feedback divider. The PLL generates a 3.35 GHz

to 4.05 GHz clock signal that is phase-locked to the input reference

multiplied by the feedback divider value.

The PFD of the PLL drives a charge pump that increases, decreases,

or holds constant the charge stored on the loop filter capacitors

(both internal and external). The stored charge results in a voltage

that sets the output frequency of the VCO. The feedback loop of

the PLL causes the VCO control voltage to vary in such a way as

to phase lock the PFD input signals.

The PLL has a VCO with 128 frequency bands spanning a range

of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the

actual operating frequency within a particular band depends on

the control voltage that appears on the loop filter capacitor.

The control voltage causes the VCO output frequency to vary

linearly within the selected band. This frequency variability allows

the control loop of the PLL to synchronize the VCO output signal

with the reference signal applied to the PFD. Selection of the VCO

frequency band (as well as gain adjustment) occurs automatically

as part of the automatic VCO calibration process of the device,

which initiates at power-up (or reset). VCO calibration centers

the dc operating point of the VCO control signal. During VCO

calibration, the output drivers provide a static dc signal.

The feedback divider (N-divider) sets the frequency multiplication

factor of the PLL in integer steps over a 20-bit range. Note that the

N-divider has a lower limit of 32.

Loop Filter

The charge pump in the PFD delivers current to the loop filter

(see Figure 24). The components primarily responsible for the

bandwidth of the loop filter are external and connect between

Pin 16 and Pin 17.

The internal portion of the loop filter has two configurations: one

is for low loop bandwidth applications (~170 Hz) and the other is

for medium (~20 kHz)/high (~75 kHz) bandwidth applications.

The low loop bandwidth condition applies when the feedback

medium/high loop bandwidth configuration is in effect. The

feedback divider value depends on the configuration of the Ax

and Yx pins per Table 8.

TO

VCO

3k

Ω

FILTER

53pF

C1

R

AD9550

C2

375

Ω

400k

Ω

BUFFER

170pF

CONTROL

LOGIC

SWITCHES CHANGE

STATE FOR N

≥ 16384

LDO

17

16

FROM

CHARGE

PUMP

Figure 24. External Loop Filter

The bandwidth of the loop filter primarily depends on three

external components (R, C1, and C2). There are two sets of recom-

mended values for these components corresponding to the low and

medium/high loop bandwidth configurations (see Table 9).

Table 9. External Loop Filter Components

A3 to A0 Pins

R

C1

C2

Loop

Bandwidth

0001 to 1100, and 1111

6.8 kΩ

47 nF

1 µF

0.17 kHz

11101

12 kΩ

51 pF

220 nF

20 kHz

1101 to 1110

12 kΩ

51 pF

220 nF

75 kHz

1110 and the Y5 pin to Y0 pin = 111111.

To achieve the best jitter performance in applications requiring a

loop bandwidth of less than 1 kHz, C1 and C2 must have an

insulation resistance of at least 500 ΩF.

PLL Locked Indicator

The PLL provides a status indicator that appears at Pin 20

(LOCKED). When the PLL acquires phase lock, the LOCKED

pin switches to a Logic 1 state. When the PLL loses lock, however,

the LOCKED pin returns to a Logic 0 state.