R5F2M110ANDD datasheet(13/48 Pages) RENESAS

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R8C/M11A Group, R8C/M12A Group

2. Central Processing Unit (CPU)

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0010EJ0010 Rev.0.10

Page 13 of 45

Aug 25, 2010

2.8.7

Interrupt Enable Flag (I)

The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I

flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.

2.8.8

Stack Pointer Select Flag (U)

ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware

interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is

executed.

2.8.9

Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has

higher priority than IPL, the interrupt is enabled. If IPL is set to levels from 2 to 7, all maskable interrupt

requests are disabled.

2.8.10

Reserved Bit

The write value must be 0. The read value is undefined.

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