전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

WM8711SEDS/R 데이터시트(PDF) 13 Page - Wolfson Microelectronics plc

부품명 WM8711SEDS/R
상세설명  Internet Audio DAC with Integrated Headphone Amplifier
PDF  47 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8711SEDS/R 데이터시트(HTML) 13 Page - Wolfson Microelectronics plc

Back Button WM8711SEDS/R Datasheet HTML 9Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 10Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 11Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 12Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 13Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 14Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 15Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 16Page - Wolfson Microelectronics plc WM8711SEDS/R Datasheet HTML 17Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 47 page
background image
Production Data
WM8711 / WM8711L
w
PD Rev 4.4 April 2007
13
MASTER CLOCK TIMING
MCLK
t
XTIL
t
XTIH
t
XTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tXTIH
18
ns
MCLK System clock pulse width
low
tXTIL
18
ns
MCLK System clock cycle time
tXTIY
54
ns
MCLK Duty cycle
40:60
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
(Output)
DACLRC
(Output)
DACDAT
t
DLT
t
DHT
t
DL
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
tDL
0
10
ns
DACDAT setup time to
BCLCK rising edge
tDST
10
ns
DACDAT hold time from
BCLK rising edge
tDHT
10
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com