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NB3N502DEVB 데이터시트(PDF) 5 Page - ON Semiconductor |
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NB3N502DEVB 데이터시트(HTML) 5 Page - ON Semiconductor |
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5 / 7 page ![]() NB3N502DEVB http://onsemi.com 5 BOARD LAYOUT The evaluation board is constructed with Getek material with 50 W trace impedances and is designed to minimize noise, achieve high bandwidth and minimize crosstalk. Layer Stack L1 Signal L2 Ground L3 VDD L4 Signal Figure 6. NB3N502 Evaluation Board Top (Component) Layer S1 X2 S0 CLK REF X1/CLK DUT.1 DUT.4 DUT.8 DUT.7 DUT.6 DUT.5 Figure 7. NB3N502 Evaluation Board SMA – Ground Layer S1 X2 S0 CLK REF X1/CLK DUT.1 DUT.4 DUT.8 DUT.7 DUT.6 DUT.5 |
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