NB3N502DEVB datasheet(3/7 Pages) ONSEMI

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NB3N502DEVB

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1. Using the SMA Connectors

a. SMA connectors J3 and J4 (DUT.6 and DUT.7)

should be pulled to VCC for logic level HIGH,

pulled to GND for logic level LOW, and left

OPEN for logic level M.

2. Using the Slide Switches

a. Header pins JMP3 and JMP4 enable the slide

switches for the clock multiplier select lines, S0

and S1, and should be jumpered.

b. Switches SW3 (DUT.6) and SW4 (DUT.7) are

used to select the clock multiplier value (see

Table 2).

c. The H position of the slide switch asserts a

logic HIGH on the assigned pin, the L asserts a

logic LOW and the M is an open where the pin

“floats” to a mid−logic level by way of the

device’s internal pullup and pulldown resistors.

Table 2. CLOCK MULTIPLIER SELECT TABLE

S1*

SW4 (DUT.7)

S0**

SW3 (DUT.6)

Multiplier

3.33X

2.5X

L = GND, H = VDD, M = OPEN (unconnected)

*Pin S1 defaults to M when left open

** Pin S0 defaults to H when left open

Table 3. HEADER PIN CONDITIONS

Header

Slide Switch

Multiplier Control

SMA

Multiplier Control

JMP1

Open

JMP2

Open

JMP3

Jumper (Short Pins)

Open

JMP4

Jumper (Short Pins)

Open

Output Connections

Connect the CMOS/TTL outputs, REF and CLKOUT, to

the oscilloscope.

Table 4. OUTPUT CONNECTORS

Outputs

Board Connector

REF

J1 (DUT.4)

CLKOUT

J2 (DUT.5)

Figure 4. NB3N502 Logic Diagram

Crystal

Oscillator

VCO

Phase

Detector

Charge

Pump

TTL/

CMOS

Output

TTL/

CMOS

Output

Reference

Clock

Multiplier

Select

VDD

GND

X1/CLK

REF

CLKOUT

S1 S0

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