Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet

3–21

Serial Configuration Device Memory Access

© December 2009

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Fast Read Operation

The device is first selected by driving nCS low. The fast read instruction code is

followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in

during the rising edge of DCLK. Then the memory contents, at that address, is shifted

out on DATA, each bit being shifted out, at a maximum frequency of 40 MHz, during

the falling edge of DCLK.

The instruction sequence is shown in Figure 3–12.

The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out. The

whole memory can, therefore, be read with a single fast read instruction. When the

highest address is reached, the address counter rolls over to 000000h, allowing the

read sequence to be continued indefinitely.

The fast read instruction is terminated by driving nCS high at any time during data

output. Any fast read instruction is rejected during the Erase, Program, or Write

operations without any effect on the operation that is in progress .

Figure 3–12. FAST_READ Operation Timing Diagram

Note to Figure 3–12:

(1) Address bit A[23] is a don't-care bit in EPCS64. Address bits A[23..21] are don't-care bits in EPCS16. Address

bits A[23..19] are don't-care bits in EPCS4. Address bits A[23..17] are don't-care bits in the EPCS1.

nCS

DCLK

ASDI

DATA

nCS

DCLK

ASDI

DATA

0

1

2

3

4

5

6

7

8

9

10

28

29

30

31

Operation Code

Dummy Byte

24-Bit Address (1)

MSB

MSB

MSB

MSB

High Impedance

23

22

21

3

2

1

0

DATA Out 1

DATA Out 2

765432

0

1

7

6543210

7

765432

0

1

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47