LIS331DLF

Mechanical and electrical specifications

Doc ID 15101 Rev 4

11/38

2.3

Communication interface characteristics

2.3.1

SPI - serial peripheral interface

Subject to general operating conditions for Vdd and Top.

Figure 3.

1.

Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not

tested in production

2.

Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and output port

3.

When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors

Table 5.

SPI slave timing values

Symbol

Parameter

Unit

Min.

Max.

tc(SPC)

SPI clock cycle

100

ns

fc(SPC)

SPI clock frequency

10

MHz

tsu(CS)

CS setup time

6

ns

th(CS)

CS hold time

8

tsu(SI)

SDI input setup time

5

th(SI)

SDI input hold time

15

tv(SO)

SDO valid output time

50

th(SO)

SDO output hold time

9

tdis(SO)

SDO output disable time

50

SPC

CS

SDI

SDO

MSB IN

MSB OUT

LSB OUT

LSB IN

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)