ST72101 datasheet(28/85 Pages) STMICROELECTRONICS

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ST72101/ST72212/ST72213

I/O PORTS (Cont’d)

5.1.4 Register Description

5.1.4.1 Data registers

Port A Data Register (PADR)

Port B Data Register (PBDR)

Port C Data Register (PCDR)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = D7-D0

Data Register 8 bits.

The DR register has a specific behaviour accord-

ing to the selected input/output configuration. Writ-

ing the DR register is always taken in account

even if the pin is configured as an input. Reading

the DR register returns either the DR register latch

content (pin configured as output) or the digital val-

ue applied to the I/O pin (pin configured as input).

5.1.4.2 Data direction registers

Port A Data Direction Register (PADDR)

Port B Data Direction Register (PBDDR)

Port C Data Direction Register (PCDDR)

Read/Write

Reset Value: 0000 0000 (00h) (input mode)

Bit 7:0 = DD7-DD0

Data Direction Register 8 bits.

The DDR register gives the input/output direction

configuration of the pins. Each bit is set and

cleared by software.

0: Input mode

1: Output mode

5.1.4.3 Option registers

Port A Option Register (PAOR)

Port B Option Register (PBOR)

Port C Option Register (PCOR)

Read/Write

Reset Value: 0000 0000 (00h) (no interrupt)

Bit 7:0 = O7-O0

Option Register 8 bits.

For specific I/O pins, this register is not implement-

ed. In this case the DDR register is enough to se-

lect the I/O pin configuration.

The OR register allow to distinguish: in input mode

if the interrupt capability or the floating configura-

tion is selected, in output mode if the push-pull or

open drain configuration is selected.

Each bit is set and cleared by software.

Input mode:

0: floating input

1: input interrupt with or without pull-up

Output mode (only for PB0:PB7, PC0:PC5):

0: output open drain (with P-Buffer inactivated)

1: output push-pull

Output mode (only for PA0:PA7):

0: output open drain

1: reserved

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

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