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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PSD4235G2-12UT 데이터시트(PDF) 85 Page - STMicroelectronics |
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PSD4235G2-12UT 데이터시트(HTML) 85 Page - STMicroelectronics |
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85 / 124 page  PSD4235G2V I/O ports 85/124 Figure 28. Port A, B and C structure 19.22 Port D - functionality and structure Port D has four I/O pins. See Figure 29. Port D can be configured to perform one or more of the following functions: ● MCU I/O mode ● CPLD input - direct input to the CPLD, no input macrocells (IMC) Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: ● Address Strobe (ALE/AS, PD0) ● CLKIN (PD1) as input to the macrocells Flip-flops and APD counter ● PSD Chip Select input (CSI, PD2). Driving this signal high disables the Flash memory, SRAM and CSIOP. ● Write Enable high-byte (WRH, PD3) input, or as DBE input from a MC68HC912. DATA OUT Register DQ DQ WR WR MCELLA7-MCELLA0 (Port A) MCELLB7-MCELLB0 (Port B) Ext.CS (Port C) ENABLE PRODUCT TERM (.OE) READ MUX P D B CPLD - INPUT DIR Register INPUT MACROCELL ENABLE OUT DATA IN OUTPUT MUX PORT Pin DATA OUT AI04936 OUTPUT SELECT |
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