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Datasheet

Features

6.2.1

Normal State

This is the normal operating state for the processor.

6.2.2

HALT and Enhanced HALT Powerdown States

The Prescott processor supports the HALT or Enhanced HALT powerdown state. The Enhanced

HALT powerdown state is configured and enabled via the BIOS.

The Enhanced HALT state is a lower power state as compared to the Stop Grant State.

If Enhanced HALT is not enabled, the default powerdown state entered will be HALT. Refer to the

sections below for details about the HALT and Enhanced HALT states.

6.2.2.1

HALT Powerdown State

HALT is a low power state entered when all the logical processors have executed the HALT or

MWAIT instructions. When one of the logical processors executes the HALT instruction, that

logical processor is halted, however, the other processor continues normal operation. The processor

will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0]

(NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III:

System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process bus snoops.

6.2.2.2

Enhanced HALT Powerdown State

Enhanced HALT is a low power state entered when all logical processors have executed the HALT

or MWAIT instructions and Enhanced HALT has been enabled via the BIOS. When one of the

logical processors executes the HALT instruction, that logical processor is halted; however, the

other processor continues normal operation.

The processor will automatically transition to a lower frequency and voltage operating point before

entering the Enhanced HALT state. Note that the processor FSB frequency is not altered; only the

internal core frequency is changed. When entering the low power state, the processor will first

switch to the lower bus ratio and then transition to the lower VID.

While in Enhanced HALT state, the processor will process bus snoops.

The processor exits the Enhanced HALT state when a break event occurs. When the processor exits

the Enhanced HALT state, it will first transition the VID to the original value and then change the

bus ratio back to the original value.

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