PSD813F2V datasheet(64/109 Pages) STMICROELECTRONICS

64 / 109 page

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Product(s)

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Product(s)

PSD813F2V, PSD854F2V

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Doc ID 10552 Rev 3

For Users of the HC11 (or compatible)

The HC11 turns off its E clock when it sleeps.

Therefore, if you are using an HC11 (or compati-

ble) in your design, and you wish to use the Pow-

er-down mode, you must not connect the E clock

to CLKIN (PD1). You should instead connect a

crystal oscillator to CLKIN (PD1). The crystal oscil-

lator frequency must be less than 15 times the fre-

quency of AS. The reason for this is that if the

frequency is greater than 15 times the frequency

of AS, the PSD keeps going into Power-down

mode.

Other Power Saving Options

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the PSD Chip Select Input (CSI,

PD2) feature, they are enabled by setting bits in

PMMR0 and PMMR2.

Figure 33. Enable Power-down Flow Chart

PLD Power Management

The power and speed of the PLDs are controlled

by the Turbo Bit (Bit 3) in PMMR0. By setting the

bit to '1,' the Turbo mode is off and the PLDs con-

sume the specified standby current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time is increased by

10ns after the Turbo Bit is set to '1' (turned off)

when the inputs change at a composite frequency

of less than 15 MHz. When the Turbo Bit is reset

to '0' (turned on), the PLDs run at full power and

speed. The Turbo Bit affects the PLD’s DC power,

AC power, and propagation delay.

Blocking MCU control signals with the bits of

PMMR2 can further reduce PLD AC power con-

sumption.

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

AI02892

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