PSD813F2V datasheet(79/109 Pages) STMICROELECTRONICS

79 / 109 page

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PSD813F2V, PSD854F2V

Doc ID 10552 Rev 3

Note: 1. Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC –0.1. VIH1 is valid at or above 0.8VCC.

2. CSI deselected or internal PD is active.

3. PLD is in non-Turbo mode, and none of the inputs are switching.

4. Please see Figure 36., page 72 for the PLD current calculation.

5. IOUT = 0mA

Figure 40. Input to Output Disable / Enable

VHYS

Reset Pin Hysteresis

0.3

VLKO

VCC (min) for Flash Erase and

Program

1.5

2.2

VOL

Output Low Voltage

IOL = 20µA, VCC = 3.0 V

0.01

0.1

IOL = 4mA, VCC = 3.0 V

0.15

0.45

VOH

Output High Voltage

IOH = –20µA, VCC = 3.0 V

2.9

2.99

IOH = –1mA, VCC = 3.0 V

2.7

2.8

ILI

Input Leakage Current

VSS < VIN < VCC

–1

±0.1

µA

ILO

Output Leakage Current

0.45 < VIN < VCC

–10

±5

µA

ICC (DC)

(Note 5)

Operating

Supply

Current

PLD Only

PLD_TURBO = Off,

f = 0 MHz (Note 3)

µA/PT

PLD_TURBO = On,

f = 0 MHz

200

400

µA/PT

Flash memory

During Flash memory

WRITE/Erase Only

Read only, f = 0 MHz

SRAM

f = 0 MHz

ICC (AC)

(Note 5)

PLD AC Adder

note 4

Flash memory AC Adder

1.5

2.0

mA/

MHz

SRAM AC Adder

0.8

1.5

mA/

MHz

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

tER

tEA

INPUT

INPUT TO

OUTPUT

ENABLE/DISABLE

AI02863

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