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STR750FV1 데이터시트(PDF) 65 Page - STMicroelectronics

부품명 STR750FV1
상세설명  ARM7TDMI-S??32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
PDF  84 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR750FV1 데이터시트(HTML) 65 Page - STMicroelectronics

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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
65/84
SSP synchronous serial peripheral in slave mode (SPI or TI mode)
Subject to general operating conditions with CL ≈ 45 pF
Figure 33.
SPI configuration, slave mode with CPHA=0, single transfer
Table 39.
SSP slave mode characteristics(1)
1.
Data based on characterisation results, not tested in production.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
SPI clock frequency
SSP0
2.66 MHz
(fPLCK/12)
MHz
SSP1
tsu(NSS)
NSS input setup time w.r.t
SCK first edge
SSP0
0
ns
SSP1
0
th(NSS)
NSS input hold time w.r.t
SCK last edge
SSP0
tPCLK+15ns
SSP1
tPCLK+15ns
tNSSLQV
NSS low to Data Output
MISO valid time
SSP0
2tPCLK
3tPCLK+30 ns
SSP1
2tPCLK
3tPCLK+30 ns
tNSSLQZ
NSS low to Data Output
MISO invalid time
SSP0
2tPCLK
3tPCLK+15 ns
SSP1
2tPCLK
3tPCLK+15 ns
tSCKQV
SCK trigger edge to data
output MISO valid time
SSP0
15
SSP1
30
tSCKQX
SCK trigger edge to data
output MISO invalid time
SSP0
2tPCLK
SSP1
2tPCLK
tsu(MOSI)
MOSI setup time w.r.t SCK
sampling edge
SSP0
0
SSP1
0
th(MOSI)
MOSI hold time w.r.t SCK
sampling edge
SSP0
3tPCLK+15 ns
SSP1
3tPCLK+15 ns
NSS INPUT
CPHA=0
MOSI INPUT
MISO OUTPUT
CPHA=0
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tSCKQV(MISO)
tsu(SI)
th(SI)
MSB OUT
MSB IN
BIT OUT
LSB IN
LSB OUT
CPOL=0
CPOL=1
tsu(NSS)
th(NSS)
tSCKQX(MISO)
BIT1 IN
sample
edge
trigger
edge
trigger
edge
tNSSHQZ
z
tNSSLQV
sample
edge
z
DONT CARE
DONT CARE



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