ST10F276Z5 datasheet(202/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F276Z5

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periods within the considered time interval.

On the contrary, assuming again a noiseless PLL input and supposing that the VCO is

dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N,

where N is the number of clock periods within the considered time interval.

The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller

than a certain value depending on the PLL output frequency and on the bandwidth

characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise

component. Lastly, for N greater than a second value of N, a saturation effect is evident, so

the jitter does not grow anymore when considering a longer time interval (jitter stable

increasing the number of clock periods N). The PLL loop acts as a high pass filter for any

noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation

value corresponds to what has been called self referred long term jitter of the PLL. In

Figure 56 the maximum jitter trend versus the number of clock periods N (for some typical

CPU frequencies) is shown: The curves represent the very worst case, computed taking into

account all corners of temperature, power supply and process variations; the real jitter is

always measured well below the given worst case values.

Noise in supply and substrate

Digital supply noise adds determining elements to PLL output jitter, independent of the

multiplication factor. Its effect is strongly reduced thanks to particular care used in the

physical implementation and integration of the PLL module inside the device. In any case,

the contribution of digital noise to global jitter is widely taken into account in the curves

provided in Figure 56.

Figure 53.

ST10F276Z5 PLL jitter

N (CPU clock periods)

200

400

±5

±1

800

600

1000

1200

1400

64 MHz

±2

±3

±4

24 MHz

40 MHz

32 MHz

16 MHz

TJIT

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