MPC5604B datasheet(82/106 Pages) FREESCALE

82 / 106 page

tSUO

CC D Data valid after SCK edge Master mode

—

Slave mode

—

160

tHO

CC D Data hold time for outputs

Master mode

—

Slave mode

—

1 Operating conditions: Cout = 10 to 50 pF, Slew

IN = 3.5 to 15 ns.

2 Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK

starts before CSn is asserted. DSPI2 has only SLOW SCK available.

3 Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is

deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

4 The t

CSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay

between internal CS and internal SCK must be higher than

t

CSC to ensure positive tCSCext.

5 The t

ASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between

internal CS and internal SCK must be higher than

t

ASC to ensure positive tASCext.

6 This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

7 SCK and SOUT configured as MEDIUM pad

Table 42. DSPI characteristics1 (continued)

No.

Symbol

Parameter

DSPI0/DSPI1

DSPI2

Unit

Min

Typ

Max

Min

Typ

Max

MPC5604B 데이터시트(PDF) 82 Page - Freescale Semiconductor, Inc

MPC5604B 데이터시트(HTML) 82 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL